New Material For Nanoscale Computer Chips

New data from a Chinese-Danish collaboration shows that organic nanoscale wires could be an alternative to silicon in computer chips. The discovery has just been published in the respected scientific journal, Advanced Materials.

Nanochemists from the Chinese Academy of Sciences and the Nano-Science Center, Department of Chemistry, at the University of Copenhagen, have developed nanoscale electric contacts out of organic and inorganic nanowires. In the contact they have crossed the wires like Mikado sticks and coupled several contacts together in an electric circuit. In this way they have produced prototype computer electronics on the nanoscale.

Alternative to silicon computers

Today the foundation of our computers, mobile phones and other electronic apparatus is silicon transistors. A transistor is in principal an on- and off- contact and there are millions of tiny transistors on every computer chip. However, we are reaching the limit for how small we can make transistors out of silicon.

We already use various organic materials in, for example, flat screens, such as OLED (Organic Light Emitting Diode). The new results show how small and advanced devices made of organic materials can become. Thomas Bjørnholm, director of the Nano-Science Center, explains:

"We have succeeded in placing several transistors consisting of nanowires together on a nano device. It is a first step towards realisation of future electronic circuitry based on organic materials – a possible substitute for today’s silicon-based technologies. This offers the possibility of making computers in different ways in the future."

Danish-Chinese nanoelectronics

The researchers have used organic nanowires combined with the tin oxide nanowires in a so-called hybrid circuit. As in a Mikado game, the nanowires cross in a device consisting of 4-6 active transistor moieties. The devices have a low operational current, high mobility and good stability and that is essential in order for the material to be able to compete with silicon.

Professor Wenping Hu, Chinese Academy of Sciences is excited over the results, saying: "This work is the first significant result of our collaboration with the researchers from the Nano-Science Center. It is a good starting point for our new Danish-Chinese research centre for molecular nano-electronics and it underlines the fact that we can complement each other and that together we can achieve exciting and important results."

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'Rochester Cube' Points Way to More Powerful Chip Designs

The next major advance in computer processors will likely be the move from today's two-dimensional chips to three-dimensional circuits, and the first three-dimensional synchronization circuitry is now running at 1.4 gigahertz at the University of Rochester.

Unlike past attempts at 3-D chips, the Rochester chip is not simply a number of regular processors stacked on top of one another. It was designed and built specifically to optimize all key processing functions vertically, through multiple layers of processors, the same way ordinary chips optimize functions horizontally. The design means tasks such as synchronicity, power distribution, and long-distance signaling are all fully functioning in three dimensions for the first time.

"I call it a cube now, because it's not just a chip anymore," says Eby Friedman, distinguished professor of electrical and computer engineering at Rochester and faculty director of the pro of the processor. "This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2D chip."
Friedman, working with engineering student Vasilis Pavlidis, says that many in the integrated circuit industry are talking about the limits of miniaturization, a point at which it will be impossible to pack more chips next to each other and thus limit the capabilities of future processors'. He says a number of integrated circuit designers anticipate someday expanding into the third dimension, stacking transistors on top of each other.

But with vertical expansion will come a host of difficulties, and Friedman says the key is to design a 3-D chip where all the layers interact like a single system. Friedman says getting all three levels of the 3-D chip to act in harmony is like trying to devise a traffic control system for the entire United States—and then layering two more United States above the first and somehow getting every bit of traffic from any point on any level to its destination on any other level—while simultaneously coordinating the traffic of millions of other drivers.

Complicate that by changing the two United States layers to something like China and India where the driving laws and roads are quite different, and the complexity and challenge of designing a single control system to work in any chip begins to become apparent, says Friedman.
Since each layer could be a different processor with a different function, such as converting MP3 files to audio or detecting light for a digital camera, Friedman says that the 3-D chip is essentially an entire circuit board folded up into a tiny package. He says the chips inside something like an iPod could be compacted to a tenth their current size with ten times the speed.

What makes it all possible is the architecture Friedman and his students designed, which uses many of the tricks of regular processors, but also accounts for different impedances that might occur from chip to chip, different operating speeds, and different power requirements. The fabrication of the chip is unique as well. Manufactured at MIT, the chip must have millions of holes drilled into the insulation that separates the layers in order to allow for the myriad vertical connections between transistors in different layers.

"Are we going to hit a point where we can't scale integrated circuits any smaller? Horizontally, yes," says Friedman. "But we're going to start scaling vertically, and that will never end. At least not in my lifetime. Talk to my grandchildren about that."

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Advances Pave Way for Powerful Carbon-Based Electronics

Bypassing decades-old conventions in making computer chips, Princeton engineers developed a novel way to replace silicon with carbon on large surfaces, clearing the way for new generations of faster, more powerful cell phones, computers and other electronics.

The electronics industry has pushed the capabilities of silicon -- the material at the heart of all computer chips -- to its limit, and one intriguing replacement has been carbon, says Stephen Chou, professor of electrical engineering. A material called graphene -- a single layer of carbon atoms arranged in a honeycomb lattice -- could allow electronics to process information and produce radio transmissions 10 times better than silicon-based devices.

Until now, however, switching from silicon to carbon has not been possible because technologists believed they needed graphene material in the same form as the silicon used to make chips: a single crystal of material eight or 12-inches wide. The largest single-crystal graphene sheets made to date have been no wider than a couple millimeters, not big enough for a single chip. Chou and researchers in his lab realized that a big graphene wafer is not necessary, as long they could place small crystals of graphene only in the active areas of the chip. They developed a novel method to achieve this goal and demonstrated it by making high-performance working graphene transistors.

“Our approach is to completely abandon the classical methods that industry has been using for silicon integrated circuits,” Chou says.

Chou, along with graduate student Xiaogan Liang and materials engineer Zengli Fu, published their findings in the December 2007 issue of Nano Letters, a leading journal in the field. The research was funded in part by the Office of Naval Research.

In their new method, the researchers make a special stamp consisting of an array of tiny flat-topped pillars, each one-tenth of a millimeter wide. They press the pillars against a block of graphite (pure carbon), cutting thin carbon sheets, which stick to the pillars. The stamp is then removed, peeling away a few atomic layers of graphene. Finally, the stamp is aligned with and pressed against a larger wafer, leaving the patches of graphene precisely where transistors will be built.

The technique is like printing, Chou says. By repeating the process and using variously shaped stamps (the researchers also made strips instead of round pillars), all the active areas for transistors are covered with single crystals of graphene.

“Previously, scientists have been able to peel graphene sheets from graphite blocks, but they had no control over the size and location of the pieces when placing them on a surface,” Chou says.

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